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Minutes
of the Joint ECA Soldering Technology Committee (STC), IPC 5-23b,
and JEDEC JC13 TG9901 Committee Meeting
Tuesday,
9 October 2001 Loews Hotel, Philadelphia, PA
Wednesday, 10 October 2001 Rosen, Center Hotel, Orlando, FL
Chairman:
Mark Kwoka
|
Name
|
PI*
|
Organization
|
|
V
|
T
|
|
Voting
Members
|
| Mark
Kwoka |
M |
P |
Intersil |
| Greg
Wood |
M |
G |
American
Competitiveness Inst. |
| Stephen
Todd |
M |
P |
FCI
Electronics |
|
Absent
Voting Members
|
| Dave
Hillman |
M |
U |
Rockwell-Collins |
| Gordon
Davy |
M |
U |
Northrop
Grumman |
| Maureen
Williams |
M |
G |
NIST
|
| Kil-Won
Moon |
M |
G |
NIST
|
| Doug
Romm |
M |
P |
Texas
Instruments, Inc. |
| Nancy
Reynolds |
M |
P |
Kemet
Electronics |
| George
Wenger |
M |
U |
Lucent
Technologies |
| Jeff
Cannis |
M |
P |
Amkor
Technology, Inc. |
|
Nonvoting
Members Present
|
| Ted
Coler |
G |
P |
Vishay |
| Yan
Ma |
G |
P |
AEM,
Inc. |
| Ed
Mikoski |
S |
G |
EIA |
| Robert
Willis |
S |
G |
ECA |
| Tim
Skidmore |
G |
P |
Raytheon |
| Keith
Whitlaw |
G |
P |
Shipley
Ronal |
| Bill
Russell |
G |
U |
Raytheon |
| *
PI = Participant identification: V = voting status; M = member;
G = guest; S = staff; T = participant type; P = producer; U = user;
G = general participant |
1
Committee organization and procedures
1.1 Membership and attendance
Self-introductions
were made, attendance taken, and it was determined that a quorum was
not present.
1.2 Approval of
the Agenda
The Committee
unanimously accepted the Agenda as presented.
1.3 Approval of
the Minutes
The Committee
unanimously accepted the Minutes of the last meeting as written.
1.4 Review of the
Committee's scope
No review
was needed.
2 Old business
2.1 Review/status
of ANSI J/STD-001-C
ANSI J/STD-001-C
was published March 2000 and there has been no revision activity started
yet.
2.2 Review of ANSI
J/STD-002-B
2.2.1 "Active wetting" results on new samples
At the Orlando
meeting, Dave Hillman informed the group that all of the split lot components
that were assembled onto circuit boars at Rockwell have passed the Class
3 Requirements of J Std-001C.
The results have been added to the chart below.
ZERO
HOUR STEAM AGE Solderability Test Results
| |
TESTER
1
(45 deg,
ROL0)
|
TESTER
2
(90 deg
ROL0)
|
TESTER
3
(Actiec
2)
|
Board
Assembly
|
| |
J Std-002A
|
“Active Wet”
|
J Std-002A
|
“Active Wet”
|
J Std-002A
|
“Active Wet”
|
J Std-002A
|
Active Wet
|
|
8 ld SOIC
|
0/16 0/4
|
0/16
0/4
|
7/40 3/5
|
9/40
4/5
|
0/ 20 0/5
|
0 / 20
0 /5
|
Pass
|
Pass
|
|
44ld MQFP
|
53 /55 5/5
|
51/55
5/5
|
2/110 1/5
|
2/110
1/5
|
55/55 5/5
|
55/55
5 /5
|
Pass
|
Pass
|
|
3 ld To-220
|
0/15 0/5
|
0/15
0/5
|
0/15
0/5
|
0/15
0/5
|
0/15
0/5
|
0 /15
0 /5
|
Pass
|
Pass
|
|
208 ld MQFP
|
0/260 0/5
|
0/260
0/5
|
5/468 2/4
|
5/468
2/4
|
0/260 0/5
|
0/260
0 /5
|
Pass
|
Pass
|
EIGHT
HOUR STEAM AGE Solderability Test Results
| |
TESTER
1
(45 deg Angle, ROL0)
|
TESTER
2 (90 deg
Angle, ROL0)
|
TESTER
3
(Actiec
2)
|
Board
Assembly
|
| |
J Std-002A
|
“Active Wet”
|
J Std-002A
|
“Active Wet”
|
J Std-002A
|
“ActiveWet”
|
J Std-002A
|
Active Wet
|
|
8 ld SOIC
|
15/20 5/5
|
14/20
5/5
|
9/40
4/5
|
16/40 5/5
|
1/ 20
1/5
|
1 / 20
1/5
|
Pass
|
Pass
|
|
44 ld MQFP
|
49 /55 5/5
|
48/55
5/5
|
15/110
5/5
|
36/110 5/5
|
55/55 5/5
|
55 /55
5/5
|
Pass
|
Pass
|
|
3 ld To-220
|
6/15
3/5
|
12/15
5/5
|
0/15
0/5
|
0/15
0/5
|
0/15
0/5
|
15 /15
5/5
|
Pass
|
Pass
|
|
208 ld MQFP
|
29/260 3/5
|
92/260
5/5
|
343/520 5/5
|
422/520
5/5
|
138/260 4/5
|
190/260 5/5
|
Pass
|
Pass
|
A discussion of
these data ensued. These final board level assembly results show that
both of the dip and look solderability test requirements are over rejecting
marginal components when 8 hr steam preconditioning is applied prior
to the dip and look test.. None of these components failed J Std-001C
Class 3 requirements at the board level. The ROL0 flux data do show
that it is likely that more reject leads on rejected units would be
obtained using the active wetting requirements. However, there is no
difference in the overall conclusions reached using either the active
wetting or current J Std-002A requirements. Both tests over reject marginal
product. The ROL1 data (Actiec 2) indicates no difference in the overall
conclusions reached using either the active wetting or current J-STD-002A
requirements on all package styles except the 8 hour steam aged, 3 lead
TO-220 cell. With the board level assembly referee now complete, the
group felt that the active wetting proposal does not offer any increased
accuracy, reduced test variation or increased ease of use of the J Std-002
test method and this activity will be dropped.
2.2.2. Current Data
Summary Supporting Change to Actiec 2 Flux
1) Analysis
of wetting balance data comparing Actiec 2 with R flux from Fall '99
and Spring '00 showed less wetting balance parameter variation with
the Actiec 2 flux compared to R flux.
2) George Wenger
4 lead tabs exhibited poor solderability and were rejected during solderability
testing using both R and Actiec 2 flux . The proposed Actiec 2 flux
did not allow the poor soldering shields to pass the dip and look test.
3) NIST metal shield
data which exhibited a range of active wetting, all failed the dip and
look test using either R or Actiec 2 or Actiec 5 fluxes. Again poor
soldering shields did not pass the solderability test using the Actiec
2 flux.
4) IPC/STC/JEDEC
Joint Test Plan underway.
2.2.3 IPC 5-23b/ EIA - STC/ JEDEC JC 13 TG9901 Joint Test Plan
Mr. Kwoka
briefly reviewed the Joint Test Plan which has been agreed to between
the IPC 5-23b, EIA STC and the JEDEC JC 13 TG9901. The test plan is
being run to validate and determine choices of Solder Dwell Time(3 sec
vs 5 sec), Solder Test Flux (R vs Actiec 2) and Solder Test Temperature
( 235 vs 245 C).
Experimental units used for this study are "marginal" 44ld
MQFP, 8ld SOIC, 14ld CERDIP, 14ld PDIP, 2 ld Chip Caps. The testers
participating in the study are Kon Lin, Dave Hillman, George Wenger,
Kil-Won Moon/Maureen Williams, and Greg Wood. Greg wood of ACI presented
his results which have been included in the table below. All three testers
have now completed their evaluations. In Addition, at the Orlando meeting
Dave Hillman informed the group that all of the split lot components
that were assembled onto circuit boards passed J Std-001C Class 3 requirements.
All cells had some failures. We will now execute the data analysis before
drawing any conclusions.
ACTION ITEM: Mr. Kwoka to contact Bill Russell and send the finished
test plan to Mr. Russell for analysis. Mr. Russell to complete the analysis
for presentation at the next meeting.
2.2.4 Soldering Iron Test
Mr. Hillman conducted a poll on TechNet and had four respondents. One
out of four indicted they still used the soldering iron test. Mr. Singleton
responded via email that his company uses the test. The group agreed
to consider a draft proposal of the test method based on the IEC and
Mil-Std documents.
ACTION ITEM: Mr.
Hillman to draft a straw-man solder iron test method for the next meeting.
2.3 Lead-free testing
and requirements and STC role/responsibilities
2.3.1 Lead Free
Trends
Mr. Kwoka discussed some of the lead free efforts that are currently
underway in the industry. NEMI
Is currently investigating lead free alternative solders and also has
an active whisker test task group working on a whisker test method for
use to determine the propensity of a sample/component to form whiskers.
Also, the Lead Free Component Focus Group has just completed it's evaluation
of 4 component finishes across 3 circuit board finishes and using 3
solder alloys. These results were presented at the IPC Fall Conference
in Orlando, FL. Despite much discussion about lead free, to date there
has not been much demand for lead free component termination finish.
|
IPC/EIA/JEDEC
Joint Solderability Test Specification Design Experiment
|
|
J
Std-002 “Dip and Look” Test Method A Category 1 ( No Steam Age
)
|
|
Component
Type, I/O & Surface Finish
|
Board level Assembly |
ROL0
( Type R ) 235C 3 Sec
|
ROL1
(Actiec 2 ) 235C 3 Sec
|
| |
|
Tester
1
|
Tester
2
|
Tester
3
|
Tester
1
|
Tester
2
|
Tester
3
|
|
Variable
Resistor 2 I/O Ag
|
0/6; 0/3 |
0/10;
0/5
|
2/5;
2/5
|
1/5 |
1/10;
1/5
|
4/5;
4/5
|
4/5 |
|
SOIC
8 I/O NiPd
|
0/24; 0/3 |
2/80;
2/5
|
0/20;
0/5
|
1/11; 1/5 |
0/80;
0/5
|
0/20;
0/5
|
1/17; 1/5 |
|
MQFP
44 I/O SnPb
|
0/132; 0/3 |
3/110;
1/5
|
0/55;
0/5
|
5/49; 4/5 |
0/110;0/5
|
0/55;
0/5
|
7/37; 4/4 |
|
PDIP
14 I/O SnPb
|
0/42; 0/3 |
0/70;
0/5
|
1/35;
1/5
|
18/70; 5/5 |
0/70;
0/5
|
1/35;
1/5
|
13/20; 4/5 |
|
Cerdip
14 I/O Sn
|
0/42; 0/3 |
0/70;
0/5
|
0/35;
0/5
|
1/70; 1/5 |
0/70;
0/5
|
0/35;
0/5
|
6/20; 3/5 |
| |
|
Component
Type, I/O and Surface Finish
|
Board level Assembly |
ROL0
( Type R ) 235C 5 Sec
|
ROL1
(Actiec 2 ) 235C 5 Sec
|
| |
|
Tester
1
|
Tester
2
|
Tester
3
|
Tester
1
|
Tester
2
|
Tester
3
|
|
Variable
Resistor 2 I/O Ag
|
0/6; 0/3 |
0/10;
0/5
|
1/5;
1/5
|
0/5 |
0/10;
0/5
|
0/5;
0/5
|
2/5 |
|
SOIC
8 I/O NiPd
|
0/24; 0/3 |
0/80;
0/5
|
0/20;
0/5
|
0/11; 0/5 |
0/80;
0/5
|
0/20;
0/5
|
0/20; 0/5 |
|
MQFP
44 I/O SnPb
|
0/132; 0/3 |
0/110;
0/5
|
0/55;
0/5
|
2/27; 1/3 |
0/110;0/5
|
0/55;
0/5
|
2/43; 1/5 |
|
PDIP
14 I/O SnPb
|
0/42; 0/3 |
0/70;
0/5
|
0/35;
0/5
|
14/70; 5/5 |
0/70;
0/5
|
0/35;
0/5
|
15/20; 4/5 |
|
Cerdip
14 I/O Sn
|
0/42; 0/3 |
0/70;
0/5
|
2/35;
1/5
|
1/70; 1/5 |
0/70;
0/5
|
0/35;
0/5
|
4/19; 2/5 |
| |
|
Component
Type, I/O and Surface Finish
|
Board level Assembly |
ROL0
( Type R ) 240C 3 Sec
|
ROL1
(Actiec 2 ) 240C 3 Sec
|
| |
|
Tester
1
|
Tester
2
|
Tester
3
|
Tester
1
|
Tester
2
|
Tester
3
|
|
Variable
Resistor 2 I/O Ag
|
0/6; 0/3 |
0/10;
0/5
|
5/5
|
1/5 |
1/10;
1/5
|
4/5
|
0/5 |
|
SOIC
8 I/O NiPd
|
0/24; 0/3 |
0/80;
0/5
|
1/20;
1/5
|
0/9; 0/4 |
0/80;
0/5
|
0/20;
0/5
|
0/20; 0/5 |
|
MQFP
44 I/O SnPb
|
0/132; 0/3 |
0/110;
0/5
|
0/55;
0/5
|
1/44; 1/4 |
0/110;0/5
|
0/55;
0/5
|
7/41; 3/4 |
|
PDIP
14 I/O SnPb
|
0/42; 0/3 |
0/70;
0/5
|
1/35;
1/5
|
13/70; 4/5 |
0/70;
0/5
|
1/35;
1/5
|
3/70; 2/5 |
|
Cerdip
14 I/O Sn
|
0/42; 0/3 |
0/70;
0/5
|
3/35;
2/5
|
0/70; 0/5 |
0/70;
0/5
|
1/35;
1/5
|
1/56; 1/5 |
| |
|
Component
Type, I/O and Surface Finish
|
Board level Assembly |
ROL0
( Type R ) 240C 5 Sec
|
ROL1
(Actiec 2 ) 240C 5 Sec
|
| |
|
Tester
1
|
Tester
2
|
Tester
3
|
Tester
1
|
Tester
2
|
Tester
3
|
|
Variable
Resistor 2 I/O Ag
|
0/6; 0/3 |
0/10;
0/5
|
5/5
|
0/5 |
|
3/5
|
1/5 |
|
SOIC
8 I/O NiPd
|
0/24; 0/3 |
0/80;
0/5
|
0/20;
0/5
|
1/11; 1/3 |
|
0/20;
0/5
|
0/68; 0/5 |
|
MQFP
44 I/O SnPb
|
0/132; 0/3 |
0/110;
0/5
|
4/55;
2/5
|
10/55; 5/5 |
|
0/55;
0/5
|
3/37; 2/4 |
|
PDIP
14 I/O SnPb
|
0/42; 0/3 |
0/70;
0/5
|
6/35;
2/5
|
4/56; 1/4 |
|
0/35;
0/5
|
10/70; 4/5 |
|
Cerdip
14 I/O Sn
|
0/42; 0/3 |
0/70;
0/5
|
1/35;
1/5
|
1/70; 1/5 |
|
0/35;
0/5
|
0/70; 0/5 |
| |
|
Component
Type, I/O and Surface Finish
|
Board level Assembly |
ROL0
( Type R ) 245C 3 Sec
|
ROL1
(Actiec 2 ) 245C 3 Sec
|
| |
|
Tester
1
|
Tester
2
|
Tester
3
|
Tester
1
|
Tester
2
|
Tester
3
|
|
Variable
Resistor 2 I/O Ag
|
0/6; 0/3 |
1/10;
1/5
|
0/5;
0/5
|
1/5 |
0/10;
0/5
|
0/5;
0/5
|
0/5 |
|
SOIC
8 I/O NiPd
|
0/24; 0/3 |
0/80;
0/5
|
0/20;
0/5
|
2/18; 2/5 |
0/80;
0/5
|
0/20;
0/5
|
4/20; 1/5 |
|
MQFP
44 I/O SnPb
|
0/132; 0/3 |
0/110;
0/5
|
0/55;
0/5
|
3/44; 2/5 |
0/110;0/5
|
0/55;
0/5
|
3/34; 1/4 |
|
PDIP
14 I/O SnPb
|
0/42; 0/3 |
0/70;
0/5
|
4/35;
4/5
|
9/70; 3/5 |
0/70;
0/5
|
5/35;
3/5
|
13/70; 4/5 |
|
Cerdip
14 I/O Sn
|
0/42; 0/3 |
0/70;
0/5
|
0/35;
0/5
|
1/70; 1/5 |
0/70;
0/5
|
0/35;
0/5
|
1/63; 1/5 |
| |
|
Component
Type, I/O and Surface Finish
|
Board level Assembly |
ROL0
( Type R ) 245C 5 Sec
|
ROL1
(Actiec 2 ) 245C 5 Sec
|
| |
|
Tester
1
|
Tester
2
|
Tester
3
|
Tester
1
|
Tester
2
|
Tester
3
|
|
Variable
Resistor 2 I/O Ag
|
0/6; 0/3 |
0/10;
0/5
|
0/5;
0/5
|
1/5 |
0/10;
0/5
|
0/5;
0/5
|
0/5 |
|
SOIC
8 I/O NiPd
|
0/24; 0/3 |
0/80;
0/5
|
0/20;
0/5
|
2/18; 1/4 |
0/80;
0/5
|
0/20;
0/5
|
0/20; 0/5 |
|
MQFP
44 I/O SnPb
|
0/132; 0/3 |
0/110;
0/5
|
0/55;
0/5
|
7/55; 2/5 |
0/110;0/5
|
0/55;
0/5
|
3/45; 2/5 |
|
PDIP
14 I/O SnPb
|
0/42; 0/3 |
0/70;
0/5
|
9/35;
2/5
|
12/70; 4/5 |
0/70;
0/5
|
3/35;
2/5
|
15/70; 5/5 |
|
Cerdip
14 I/O Sn
|
0/42; 0/3 |
0/70;
0/5
|
0/35;
0/5
|
1/70; 1/5 |
0/70;
0/5
|
0/35;
0/5
|
0/63; 0/5 |
2.4 JEDEC Revision
of Mil STD883/2003, Mil Std750/2026 and participation in ANSI J/STD-002-B
revision
Mr. Kwoka discussed
the results of a "survey" of the JEDEC JC 13 regarding a proposal
of changing the J Std-002A as follows:
Solder Immersion
Time : From 5 seconds TO 3 seconds
Flux : From ROL0 TO ROL1 (Actiec 2)
This survey was
on the JEDEC electronic voting machine. A total of 20 responses were
received. 9 respondents indicated that they would accept these proposed
changes if this were a ballot. 6 respondents offered editorial changes
and 5 respondents said they would reject the proposal. The reasons for
the 5 rejections were as follows:
1) Unknown impact on already tested finished goods. Retesting required.
2) Changes would require more testing, tighter criteria, increased test
equipment capability.
3) Chloride activator is radical addition to flux and may let marginally
bad parts pass test. The term "colophony" is not well defined.
4) 3 sec immersion time is too fast and will not allow complete dissolution
of some commonly used termination finishes like palladium.
5) 235C is too cold to show internal reflow problems associated with
some complex components.
Dave Hillman has checked BADER's charts and it does appear that 3 seconds
may not be sufficient time for NiPd dissolution and that 5 seconds may
be a more robust condition. We will check into the other four assertions,
achieve consensus and respond to each commenter. Mr. Kwoka also reiterated
that the JEDEC people have been very cooperative and are working in
good faith to review the J Std-002 and adopt as much as possible the
J Std-002 into the Mil Std 883 TM 2003 and the Mil Std 750 TM 2026.
ACTION ITEM: Mr.
Hillman to clarify the "type of colophony" used in the manufacture
of Actiec 2 and also determine if Actiec 2 is a trademark.
3 New business
3.1 Liason with
P-9 Committee
Mr Skidmore, chairman
of the ECA P-9 Test Methods Committee for Passives inquired whether
the STC would be the natural place for specifications concerning resistance
to soldering heat and dissolution of metalization. The STC would be
the natural place for such specifications. The P-9 Committee administers
documents in the " TM - 186 series ", some of which contain
test methods for soldering related activities. Mr. Skidmore will discuss
this further with the P-9 committee.
3.2 ECA liason with
JEDEC and IPC regarding J-Std-002
Mr Mikoski inquired about how the STC operates and where we perceive
the "home" of the STC resides. The STC is an ECA committee
and resides in the ECA. However, over the years, the work being done
by both the STC and the IPC 5-23b committee has overlapped significantly.
Testing evaluations are, and were, conducted by members of both committees'
that were involved in drafting the Joint Standard J Std-002. The IPC
has taken the lead in the publishing logistics of the J Std-002. It
became more convenient and cost effective to mutually agree to meet
at a single location and conduct joint meetings. We chose to convene
at the IPC since the 5-23b committee would also meet during a larger
IPC conference/show and this would improve attendance. While more convenient
for active STC members, this practice has made it difficult for other
ECA members to participate in the Soldering Technology Committee activities.
As a result, we will stagger our bi annual meeting venues. One meeting
will occur jointly with IPC and one meeting will occur with the ECA.
Mr. Mikoski also
inquired about the Memorandum of Understanding with the IPC regarding
publication, distribution, website posting and royalties associated
with the J Std-002.
ACTION ITEM: Mr.
Kwoka agreed to put Mr. Mikoski in touch with Jack Crawford and Dave
Bergman of the IPC as well as with Ingrid Taylor at JEDEC so they can
discuss and resolve this issue.
At the Orlando meeting,
Dave Bergman of IPC mentioned that the IPC has an understanding with
JEDEC.
The IPC would prefer that ECA and JEDEC first discuss and resolve issues
associated with the J Std-002 before discussing same with IPC.
4 Selection of next meetings
The next
meeting will be on 16 April 2002 in Albuquerque, NM at the ECA meeting
from 1-5 pm.
Ms. Williams will forward the meeting notice.
ACTION ITEM¾C.Williams to make meeting arrangements and distribute.
5 Adjournment
The Committee
moved, seconded, and unanimously agreed to adjourn at 4:00PM.
6 Action items
· Mr. Kwoka to contact Bill Russell and send the finished test
plan to Mr. Russell for analysis.
· Mr. Russell to complete the analysis for presentation at the
next meeting.
· Mr. Hillman to draft a straw-man solder iron test method for
the next meeting
· Mr. Hillman to clarify the "type of colophony" used
in the manufacture of Actiec 2 and also determine if Actiec 2 is a trademark.
· Mr. Kwoka agreed to put Mr. Mikoski in touch with Jack Crawford
and Dave Bergman of the IPC as well as with Ingrid Taylor at JEDEC so
they can discuss and resolve this issue.
· C.Williams to make meeting arrangements and distribute.
This meeting was
conducted in accordance with the EIA legal guidelines and the EIA manual
of organization and procedure.
This meeting was
conducted in accordance with the EIA legal guidelines and the EIA manual
of organization and procedure.
Mark Kwoka, Chairperson
Signature on file
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