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Minutes of the Joint Soldering Technology Committee (STC), JEDEC JC13 TG9901 and the
IPC 5-23b Meeting at the Hyatt Regency San Diego Convention Center
Monday, 15 January 2001

Chairman: Mark Kwoka

Name
PI*
Organization
V
T
Voting members
Jeff Cannis M P Amkor Technology, Inc.
Dave Hillman M U Rockwell-Collins
Mark Kwoka M U Intersil
Gordon Davy M U Northrop Grumman
Maureen Williams M G NIST
Kil-Won Moon M G NIST
Greg Wood M G American Competitiveness Inst.
Doug Romm M P Texas Instruments, Inc.
Nancy Reynolds M P Kemet Electronics
George Wenger M U Lucent Technologies
Stephen Todd M P FCI Electronics
Nonvoting members
Harry Spence G P Microsemi Corp.
Bill Bennet G P Cypress Semiconductor
Mel Parrish G P NIST
Don Cullen G P MacDermid Inc.
Del Currier G P Ambitech Inc.
Jim Martin G P Shipley Ronal
Keith Whitlaw G P Shipley Ronal
Bill Russell G U Raytheon
* PI = Participant identification: V = voting status; M = member; G = guest; S = staff; T = participant type; P = producer; U = user; G = general participant

1 Committee organization and procedures
1.1 Membership and attendance

Self-introductions were made, attendance taken, and it was determined that a quorum was present.

1.2 Approval of the Agenda

The Committee unanimously accepted the Agenda as presented.

1.3 Approval of the Minutes

The Committee unanimously accepted the Minutes of the last meeting as written.

1.4 Review of the Committee's scope

No review was needed.

2 Old business
2.1 Review/status of ANSI J/STD-001-C

ANSI J/STD-001-C was published March 2000 and there has been no revision activity started yet. IPC J-STD-001-C Handbbook and re-certification activity is underway as reported by Mel Parrish.

2.2 Review of ANSI J/STD-002-B

2.2.1 "Active wetting" results on new samples

Ms. Williams and Mr. Moon presented their data(attachment 1 ) on the active wetting evaluation using Actiec 2 flux, which are included in the charts below.

ZERO HOURS STEAM AGE Solderability Test Results

 

     TESTER  1(45 deg

               Angle, ROL0)

    TESTER  2 (90 deg

                Angle, ROL0)

     TESTER  3 (Actiec 2)

 

J Std-002A

“Active Wet”

J Std-002A

“Active Wet”

J Std-002A

“Active Wet”

8 ld   SOIC

 0/16    0/4

 0/16      0/4

7/40     3/5

 9/40      4/5

0/ 20   0/5

  0 / 20   0 /5

44ld

MQFP

53 /55  5/5

51/55     5/5

 2/110  1/5

 2/110    1/5

55/55  5/5

 55/55    5 /5

  3 ld To-

     220

 0/15    0/5

  0/15     0/5

 0/15     0/5

 0/15       0/5

 0/15     0/5

  0 /15    0 /5

 208 ld MQFP

 0/260  0/5

  0/260     0/5

5/468    2/4

 5/468      2/4

  0/260  0/5

   0/260  0 /5

EIGHT HOUR STEAM AGE Solderability Test Results

 

     TESTER  1 (45 deg
                   Angle, ROL0)

    TESTER  2 (90 deg
                 Angle,  ROL0)

     TESTER  3 (Actiec 2)

 

J Std-002A

“Active Wet”

J Std-002A

“Active Wet”

J Std-002A

“ActiveWet”

  8 ld SOIC

15/20    5/5

   14/20     5/5

  9/40    4/5

 16/40   5/5

 1/ 20    1/5

 1 / 20     1/5

 44 ld MQFP

49 /55   5/5

   48/55     5/5

  15/110  5/5

 36/110  5/5

 55/55   5/5

 55 /55    5/5

  3 ld To-220

  6/15    3/5

  12/15      5/5

  0/15      0/5

 0/15     0/5

  0/15    0/5

 15 /15    5/5

 208 ld MQFP

29/260  3/5

 92/260     5/5

343/520  5/5

422/520    5/5

138/260 4/5

190/260  5/5

A discussion of these data ensued. The ROL0 flux data do show that it is likely that more reject leads on reject units are detected using the active wetting requirements. However, there is no difference in the overall conclusions reached using either the active wetting or current J Std-002A requirements. The ROL1 data (Actiec 2) indicates no difference in the overall conclusions reached using either the active wetting or current J-STD-002A requirements on all package styles except the 8 hour steam aged, 3 lead TO-220 cell. While this was only one cell that did not agree, the group felt another round of experimentation using the ROL1 flux with additional testers would allow a resolution of this evaluation. Also, the board assembly results using steam aged samples will be required.

ACTION ITEM: Mr. Kwoka to send new steam aged/no steam aged samples to Mr. Hillman. Mr Kwoka will also send new sample sets (steam/no steam) to Mssr. Wenger and Wood along with a new test plan. Mr. Hillman to complete the steam/no steam board assembly and present at next meeting.

2.2.2. Current Data Summary Supporting Change to Actiec 2 Flux

1) Analysis of wetting balance data comparing Actiec 2 with R flux from Fall '99 and Spring '00 showed less wetting balance parameter variation with the Actiec 2 flux compared to R flux.

2) George Wenger 4 lead tabs exhibited poor solderability and were rejected during solderability testing using both R and Actiec 2 flux . The proposed Actiec 2 flux did not allow the poor soldering shields to pass the dip and look test.

3) NIST metal shield data which exhibited a range of active wetting, all failed the dip and look test using either R or Actiec 2 or Actiec 5 fluxes. Again poor soldering shields did not pass the solderability test using the Actiec 2 flux.

4) IPC/STC/JEDEC Joint Test Plan underway.

2.2.3 IPC 5-23b/ EIA - STC/ JEDEC JC 13 TG9901 Joint Test Plan

Mr. Kwoka briefly reviewed the Joint Test Plan which has been agreed to between the IPC 5-23b, EIA STC and the JEDEC JC 13 TG9901. The test plan is being run to validate and determine choices of Solder Dwell Time(3 sec vs 5 sec), Solder Test Flux (R vs Actiec 2) and Solder Test Temperature ( 235 vs 245 C).
Experimental units used for this study are "marginal" 44ld MQFP, 8ld SOIC, 14ld CERDIP, 14ld PDIP, 2 ld Chip Caps. The testers participating in the study are Kon Lin, Dave Hillman, George Wenger, Kil-Won Moon/Maureen Williams . Kil-Wan Moon and Maureen Williams of NIST presented their sample evaluations and presented their results (attachment 2). George Wenger, Kil-Wan Moon and Maureen Williams have now completed their evaluations. The results are given below. All of these "marginal samples" pass the dip and look test using ROL1, 235C and 5 sec test time. All other cells had some failures. We will wait for the remainder of the testers to complete their work before drawing any conclusions. Also the group felt that the referee board assembly should be completed for reference.
ACTION ITEM: Mr. Kwoka to send a new joint test plan sample kit to Mr. Wood to complete testing as tester 3. Mr Kwoka to send sufficient samples for 240C testing to Mssr. Williams and Moon, along with extra set-up samples. Mr. Kwoka to send sufficient samples (steam and no steam) to Mr. Hillman. Mr. Hillman to complete joint test plan board assembly cells and present results at next meeting.

2.2.4 Post Steam Age Dry

A brief review of thr Texas Instruments data, showed a 15 minute drying time is acceptable. The group agreed to insert the post steam age drying time of 15 minutes minimum into J-Std-002 Rev B.

2.2.5 Soldering Iron Test

Mr. Hillman conducted a poll on TechNet and had four respondents. One out of four indicted they still used the soldering iron test. Mr. Singleton responded via email that his company uses the test. The group agreed to consider a draft proposal of the test method based on the IEC and Mil-Std documents.

ACTION ITEM: Mr. Hillman to draft a straw-man solder iron test method for the next meeting.

2.3 Lead-free testing and requirements and STC role/responsibilities

2.3.1 Lead Free Trends in Japan
Mr. Cannis presented a review(attachments 3,4 and 5) of the lead free positions of various Japanese companies. He also discussed lead free alloy patent issues.

2.3.2 New Whisker Research
Mssr. Keith Whitlaw and Jim Martin were in attendance from Shipley Ronal. Mr. Whitlaw presented some new research on whisker growth mechanisms. The entirety of his presentation should be on the Shipley web site soon. Key points were that the tin whiskers appear to be driven from compressive stresses due to intermetallic compound growth along grain boundaries. Annealing at 150C for 1 hour appears to mitigate whisker growth. Nickel strike appears to eliminate whisker growth.

IPC/EIA/JEDEC Joint Solderability Test Specification Design Experiment

J Std-002 “Dip and Look” Test Method A Category 1 ( No Steam Age )

Component Type,  I/O and Surface Finish

ROL0 ( Type R )    235C    3 Sec

ROL1 (Actiec 2 )    235C    3 Sec

 

Tester 1

Tester 2

Tester 3

Tester 1

Tester 2

Tester 3

Variable Resistor   2 I/O   Ag

0/10; 0/5

2/5; 2/5

 

1/10; 1/5

4/5; 4/5

 

SOIC                     8 I/O  NiPd

2/80; 2/5

0/20; 0/5

 

0/80; 0/5

0/20; 0/5

 

MQFP                  44 I/O  SnPb

3/110; 1/5

0/55; 0/5

 

0/110;0/5

0/55; 0/5

 

PDIP                    14 I/O  SnPb

0/70; 0/5

1/35; 1/5

 

0/70; 0/5

1/35; 1/5

 

Cerdip                  14 I/O  Sn

0/70; 0/5

0/35; 0/5

 

0/70; 0/5

0/35; 0/5

 
 

Component Type,  I/O and Surface Finish

ROL0 ( Type R )    235C    5 Sec

ROL1 (Actiec 2 )    235C    5 Sec

 

Tester 1

Tester 2

Tester 3

Tester 1

Tester 2

Tester 3

Variable Resistor   2 I/O   Ag

0/10; 0/5

1/5; 1/5

 

0/10; 0/5

0/5; 0/5

 

SOIC                     8 I/O  NiPd

0/80; 0/5

0/20; 0/5

 

0/80; 0/5

0/20; 0/5

 

MQFP                  44 I/O  SnPb

0/110; 0/5

0/55; 0/5

 

0/110;0/5

0/55; 0/5

 

PDIP                    14 I/O  SnPb

0/70; 0/5

0/35; 0/5

 

0/70; 0/5

0/35; 0/5

 

Cerdip                  14 I/O  Sn

0/70; 0/5

2/35; 1/5

 

0/70; 0/5

0/35; 0/5

 
 

Component Type,  I/O and Surface Finish

ROL0 ( Type R )    240C    3 Sec

ROL1 (Actiec 2 )    240C    3 Sec

 

Tester 1

Tester 2

Tester 3

Tester 1

Tester 2

Tester 3

Variable Resistor   2 I/O   Ag

0/10; 0/5

 

 

1/10; 1/5

 

 

SOIC                     8 I/O  NiPd

0/80; 0/5

 

 

0/80; 0/5

 

 

MQFP                  44 I/O  SnPb

0/110; 0/5

 

 

0/110;0/5

 

 

PDIP                    14 I/O  SnPb

0/70; 0/5

 

 

0/70; 0/5

 

 

Cerdip                  14 I/O  Sn

0/70; 0/5

 

 

0/70; 0/5

 

 
 

Component Type,  I/O and Surface Finish

ROL0 ( Type R )    240C    5 Sec

ROL1 (Actiec 2 )    240C    5 Sec

 

Tester 1

Tester 2

Tester 3

Tester 1

Tester 2

Tester 3

Variable Resistor   2 I/O   Ag

0/10; 0/5

 

 

 

 

 

SOIC                     8 I/O  NiPd

0/80; 0/5

 

 

 

 

 

MQFP                  44 I/O  SnPb

0/110; 0/5

 

 

 

 

 

PDIP                    14 I/O  SnPb

0/70; 0/5

 

 

 

 

 

Cerdip                  14 I/O  Sn

0/70; 0/5

 

 

 

 

 
 

Component Type,  I/O and Surface Finish

ROL0 ( Type R )    245C    3 Sec

ROL1 (Actiec 2 )    245C    3 Sec

 

Tester 1

Tester 2

Tester 3

Tester 1

Tester 2

Tester 3

Variable Resistor   2 I/O   Ag

1/10; 1/5

0/5; 0/5

 

0/10; 0/5

0/5; 0/5

 

SOIC                     8 I/O  NiPd

0/80; 0/5

0/20; 0/5

 

0/80; 0/5

0/20; 0/5

 

MQFP                  44 I/O  SnPb

0/110; 0/5

0/55; 0/5

 

0/110;0/5

0/55; 0/5

 

PDIP                    14 I/O  SnPb

0/70; 0/5

4/35; 4/5

 

0/70; 0/5

5/35; 3/5

 

Cerdip                  14 I/O  Sn

0/70; 0/5

0/35; 0/5

 

0/70; 0/5

0/35; 0/5

 
 

Component Type,  I/O and Surface Finish

ROL0 ( Type R )    245C    5 Sec

ROL1 (Actiec 2 )    245C    5 Sec

 

Tester 1

Tester 2

Tester 3

Tester 1

Tester 2

Tester 3

Variable Resistor   2 I/O   Ag

0/10; 0/5

0/5; 0/5

 

0/10; 0/5

0/5; 0/5

 

SOIC                     8 I/O  NiPd

0/80; 0/5

0/20; 0/5

 

0/80; 0/5

0/20; 0/5

 

MQFP                  44 I/O  SnPb

0/110; 0/5

0/55; 0/5

 

0/110;0/5

0/55; 0/5

 

PDIP                    14 I/O  SnPb

0/70; 0/5

9/35; 2/5

 

0/70; 0/5

3/35; 2/5

 

Cerdip                  14 I/O  Sn

0/70; 0/5

0/35; 0/5

 

0/70; 0/5

0/35; 0/5

 

2.3 JEDEC Revision of Mil STD883/2003, Mil Std750/2026 and participation in ANSI J/STD-002-B
revision

Mr. Kwoka discussed the activities at the last JEDEC Meeting and the revision of the Joint Test Plan which has been discussed above. Mr. Kwoka also reiterated that the JEDEC people have been very cooperative and are working in good faith to review the J Std-002 and adopt as much as possible the J Std-002 into the Mil Std 883 TM 2003 and the Mil Std 750 TM 2026. Mr Spence mentioned that the JC-14 , through Nick Lycoudes, is being very open minded in considering the J Std-002 and will likely adopt the J-STD-002 if it is available free through the JEDEC web site.

3 New business

There was no new business.

4 Selection of next meetings

The Committee overwhelming agreed to meet on 8 October 2001 in Philadelphia, PA, at the ECA Engineering Summit from 1-5 pm. Mr. Tinkleman will forward the meeting notice.
ACTION ITEM¾M.Tinkleman/C.Williams to make meeting arrangements and distribute.

5 Adjournment

The Committee moved, seconded, and unanimously agreed to adjourn at 3:00PM.

6 Action items

· Mr. Kwoka to send new steam aged/no steam aged samples to Mr. Hillman. Mr Kwoka will also send new sample sets (steam/no steam) to Mssr. Wenger and Wood along with a new test plan. Mr. Hillman to complete steam/no steam board assembly and present at next meeting.
· Mr. Kwoka to send a new joint test plan sample kit to Mr. Wood to complete testing as tester 3. Mr Kwoka to send sufficient samples for 240C testing to Mssr. Williams and Moon, along with extra set-up samples. Mr. Kwoka to sufficient samples (steam and no steam) to Mr. Hillman. Mr. Hillman to complete joint test plan board assembly cells and present results at next meeting.
· Mr. Hillman to draft a straw-man solder iron test method for the next meeting.
· M.Tinkleman/C.Williams to make meeting arrangements and distribute.

This meeting was conducted in accordance with the EIA legal guidelines and the EIA manual of organization and procedure.

Mark Kwoka, Chairperson
Signature on file

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